[akd4344-a] 2007/07 - 1 - general description the akd4344-a is an evaluation board for the AK4344, 24bit and 96khz dac with dit for portable and home audio systems. the akd4344-a has the interface with akm?s a/d converter evaluation boards and the interface with digital audio systems via optical connector. therefore, it is easy to evaluate the AK4344. ordering guide akd4344-a --- AK4344 evaluation board function ? compatible with 2 types of input data interface - direct interface with akm?s a/d converter evaluation boards via 10-pin header - on-board ak4112b as dir, which accepts optical or bnc inputs ? optical output for internal dit ? bnc connector for an external clock input ? bnc connector for dac output vdd agnd opt lout rout ak4112b (dir) mclk opt clock divider generator digital in digital out 74lvc541 10pin header dsp data vcc dgnd bnc analog out AK4344 figure 1. akd4344-a block diagram * circuit diagram and pcb layout are attached at the end of this manual. a k4344 evaluation board rev.2 a kd4344- a
[akd4344-a] 2007/07 - 2 - operation sequence 1) set up the power supply lines. [vdd] (red) = 2.7 3.6v (typ. 3.3v, for AK4344) [vcc] (red) = 2.7 3.6v (typ. 3.3v, for ak4112b, for 74lvc541 and for logic) [agnd] (black) = 0v [dgnd] (black) = 0v each supply line should be distributed from the power supply unit. 2) set-up the evaluation modes, jumper pins and dip switches (see the followings.) 3) power on. when ak4112b is used, the ak4112b and AK4344 should be reset once by bringing sw2 and sw1 ?l? upon power-up. when ak4112b is not used, keep sw2 to ?l?, and the AK4344 should be reset once by bringing sw1 ?l? upon power-up. evaluation mode 1) d/a part evaluation using optical or s/pdif input use port1 (rx1: opt) or j2 (rx1: bnc). the ak4112b (dir) generates mclk, bick, lrck and sdti1 from the received data through optical connector (torx141) or bnc connector. this evaluation mode should be used for the evaluation using cd test disk. nothing should be connected to port3 (dsp). the selection of opt and bnc should be done by jp14 (rx1) jp7 lrck jp4 mclk jp12 ext di r ext di r ex t jp5 bick di r ex t jp6 sdti1 2) d/a part evaluation using 10-pin connector on the akm?s a/d evaluation board use port3 (dsp). it is able to evaluate the AK4344, connecting the 10-pin connector on the akm?s a/d evaluation board and port3 (dsp) via 10-line flat cable. mclk, bick, lrck and sdti1 are sent from the a/d converter evaluation board to the akd4344 through port3 (dsp) via 10-line flat cable. jp7 lrck jp4 mclk jp12 ext di r ext di r ex t jp5 bick di r ext jp6 sdti1 3) d/a part evaluation using port3 (dsp), and supplying all interface signals from external equipments in case of using port3 (dsp), and supplying signals (mclk, bick, lrck, sdti1) that is needed for the AK4344 from external equipments, set up as following. jp7 lrck jp4 mclk jp12 ext di r ext di r ex t jp5 bick di r ext jp6 sdti1 in case of using port3 (dsp), and supplying sdti2 from external equipments, setting of sdti2 should be done by jp8 (sdti2).
[akd4344-a] 2007/07 - 3 - other jumper pins set up (1) jp15 (vdd): vdd and vcc open: separated short: common. (the connector ?vcc? can be open.) by opening the connector ?vcc?, shorting jp15 (vdd) and supplying 3.3v to the connector ?vdd?, the connector ?vdd? can supply 3.3v to all circuits (2) jp16 (gnd): analog ground and digital ground open: separated short: common. (the connector ?dgnd? can be open.) (3) jp10 (bcfs): select the bick of the AK4344 x1: bick=128fs in case of mclk=256fs/384fs/512fs/768fs. bick=64fs in case of mclk=192fs. x2: bick=64fs in case of mclk=128fs/256fs/384fs/512fs/768fs. bick=32fs in case of mclk=192fs. bick=128fs in case of mclk=1024fs/1536fs. x4: bick=32fs in case of mclk=128fs/256fs/384fs/512fs/768fs. bick=64fs in case of mclk=1024fs/1536fs. x8: bick=32fs in case of mclk=1024fs/1536fs. (4) jp11 (div), [jp9] (clk), [jp13] (lrfs) when using j1 (ext), these jumper pins should be set according to table 1. (5) jp2 (cdto / sdti2): select the signal of cdto / sdti2 pin cdto: select the cdto sdti2: select the sdti2 (6) jp8 (sdti2): select the input of sdti2 pin port3: input the signal from port3 gnd: input the ?0? data (when jp2 (cdto / sdti2): setting is cdto, set to gnd)
[akd4344-a] 2007/07 - 4 - example for external clock setting refer to the following setting when mclk, bick and lrck are supplied to the AK4344 from j1 (ext). mode fs mclk jp11 (div) jp9 (clk) jp13 (lrfs) 512fs = 4.096mhz x2 x2 x1 768fs = 6.144mhz x3 x2 x1 1024fs = 8.192mhz x2 x2 x2 8khz 1536fs = 12.288mhz x3 x2 x2 512fs = 12.288mhz x2 x2 x1 768fs = 18.432mhz x3 x2 x1 1024fs = 24.576mhz x2 x2 x2 half 24khz 1536fs = 36.864mhz x3 x2 x2 256fs = 2.048mhz x1 x2 x1 384fs = 3.072mhz open x3 x1 512fs = 4.096mhz x2 x2 x1 8khz 768fs = 6.144mhz x3 x2 x1 256fs = 8.192mhz x1 x2 x1 384fs = 12.288mhz open x3 x1 512fs = 16.384mhz x2 x2 x1 32khz 768fs = 24.576mhz x3 x2 x1 256fs = 11.2896mhz x1 x2 x1 default 384fs = 16.9344mhz open x3 x1 512fs = 22.5792mhz x2 x2 x1 44.1khz 768fs = 33.8688mhz x3 x2 x1 256fs = 12.288mhz x1 x2 x1 384fs = 18.432mhz open x3 x1 512fs = 24.576mhz x2 x2 x1 normal 48khz 768fs = 36.864mhz x3 x2 x1 128fs = 6.144mhz open x1 x1 192fs = 9.216mhz open x3 x3 256fs = 12.288mhz x1 x2 x1 48khz 384fs = 18.432mhz open x3 x1 128fs = 12.288mhz open x1 x1 192fs = 18.432mhz open x3 x3 256fs = 24.576mhz x1 x2 x1 double 96khz 384fs = 36.864mhz open x3 x1 table 1. clock setting
[akd4344-a] 2007/07 - 5 - dip switch set up [sw3]: setting the audio data format of the ak4112b (on=?h?, off=?l?) mode sw3-3 dif2 sw3-2 dif1 sw3-1 dif0 sdti format 0 l l l 16bit, lsb justified 3 l h h 24bit, lsb justified 4 h l l 24bit, msb justified 5 h l h 24bit, i 2 s compatible default table 2. sw3: audio data format of ak4112b note. the ak4112b does not support 16bit, i 2 s compatible.
[akd4344-a] 2007/07 - 6 - the function of the toggle sw [sw1] (AK4344-pdn): resets the AK4344. keep ?h? during normal operation. the AK4344 should be reset once by bringing sw1 ?l? upon power-up. [sw2] (ak4112b-pdn): resets the ak4112b. keep ?h? during normal operation. the ak4112b should be reset once by bringing sw2 ?l? upon power-up. analog output circuit the dac of AK4344 outputs analog audio signals through j3 and j4. + c13 22u r7 220 j3 bnc-r-pc 1 2 3 4 5 r9 10k + c17 22u r13 10k r12 220 j4 bnc-r-pc 1 2 3 4 5 c100 1n c101 1n lou t rou t AK4344-lout AK4344-rout figure 2. lout/rout output circuit * akemd assumes no responsibility for the trouble when using the above circuit examples. serial control the akd4344-a can be controlled via the printer port (parallel port) of ibm-at compatible pc. connect port4 (up-i/f) to pc by 10-line flat cable packed with the akd4 344-a. take care of the direction of connector. there is a mark at pin#1. the pin layout of port4 as shown figure 3. port4 up i/f 10 9 2 1 nc cdto cdti ccl k csn gnd gnd gnd gnd gnd red figure 3. port4 pin layout
[akd4344-a] 2007/07 - 7 - control software manual set-up of evaluation board and control software 1. set up the akd4344-a according to the operating sequence located on page 2. 2. connect ibm-at compatible pc with akd4344-a by 10-line type flat cable (packed with akd4344-a). take care of the direction of 10pin header. (please install the driver in the cd-rom when this control software is used on windows 2000/xp. please refer ?installation manual of c ontrol software driver by akm device control software?. in case of windows95/98/me, this installation is not needed. this control software does not operate on windows nt.) 3. insert the cd-rom labeled ?akd4344-a evaluation kit? into the cd-rom drive. 4. access the cd-rom drive and double-click the icon of ?akd4344-a.exe? to set up the control program. 5. please evaluate according to the following. operation flow keep the following flow. 1. set up the control program according to explanation above. 2. click ?port reset? button. explanation of each buttons 1. [port reset]: set up the usb interface board (akdusbif-a). 2. [write default]: initialize the register of AK4344. 3. [all write]: write all registers that is currently displayed. 4. [function1]: dialog to write data by keyboard operation. 5. [function2]: dialog to write data by keyboard operation. 6. [function3]: the sequence of register setting can be set and executed. 7. [function4]: the sequence that is created on [function3] can be assigned to buttons and executed. 8. [function5]: the register setting that is created by [save] function on main window can be assigned to buttons and executed. 9. [save]: save the current register setting. 10. [open]: write the saved values to all register. 11. [write]: dialog to write data by mouse operation. indication of data input data is indicated on the register map. red letter indicat es ?h? or ?1? and blue one indicates ?l? or ?0?. blank is the part that is not defined in the datasheet.
[akd4344-a] 2007/07 - 8 - explanation of each dialog 1. [write dialog] : dialog to write data by mouse operation there are dialogs corresponding to each register. click the [write] button corresponding to each register to set up the dialog. if you check the check box, data becomes ?h? or ?1?. if not, ?l? or ?0?. if you want to write the input data to AK4344, click [ok] button. if not, click [cancel] button. 2. [function1 dialog] : dialog to write data by keyboard operation address box: input registers ad dress in 2 figures of hexadecimal. data box: input registers da ta in 2 figures of hexadecimal. if you want to write the input data to AK4344, click [ok] button. if not, click [cancel] button. 3. [function2 dialog] : dialog to evaluate att address box: input registers address in 2 figures of hexadecimal. start data box: input starts data in 2 figures of hexadecimal. end data box: input end data in 2 figures of hexadecimal. interval box: data is written to AK4344 by this interval. step box: data changes by this step. mode select box: *if you check this check box, data reaches end data, and returns to start data. [example] start data = 00, end data = 09 data flow: 00 01 02 03 04 05 06 07 08 09 09 08 07 06 05 04 03 02 01 00 *if you do not check this check box, data reaches end data, but does not return to start data. [example] start data = 00, end data = 09 data flow: 00 01 02 03 04 05 06 07 08 09 if you want to write the input data to AK4344, click [ok] button. if not, click [cancel] button.
[akd4344-a] 2007/07 - 9 - 4. [save] and [open] 4-1. [save] save the current register setting data. the extension of file name is ?akr?. (operation flow) (1) click [save] button. (2) set the file name and push [save] button. the extension of file name is ?akr?. 4-2. [open] the register setting data saved by [save] is written to AK4344. the file type is the same as [save]. (operation flow) (1) click [open] button. (2) select the file (*.akr) and click [open] button.
[akd4344-a] 2007/07 - 10 - 5. [function3 dialog] the sequence of register setting can be set and executed. (1) click [f3] button. (2) set the control sequence. set the address, data and interval time. set ?-1? to the address of the step where th e sequence should be paused. (3) click [start] button. then this sequence is executed. the sequence is paused at the step of interval="-1". clic k [start] button, the sequence restarts from the paused step. this sequence can be saved and opened by [save] and [open] button on the function3 window. the extension of file name is ?aks?. figure 4. window of [f3]
[akd4344-a] 2007/07 - 11 - 6. [function4 dialog] the sequence that is created on [function3] can be assigne d to buttons and executed. when [f4] button is clicked, the window as shown in figure opens. figure 5. [f4] window
[akd4344-a] 2007/07 - 12 - 6-1. [open] buttons on left side and [start] buttons (1) click [open] button and select the sequence file (*.aks). the sequence file name is displayed as shown in figure . figure 6. [f4] window(2) (2) click [start] button, then the sequence is executed. 6-2. [save] and [open] buttons on right side [save]: the sequence file names can assign be saved. the file name is *.ak4. [open]: the sequence file names assign that are saved in *.ak4 are loaded. 6-3. note (1) this function doesn't support the pause function of sequence function. (2) all files need to be in same folder used by [save] and [open] function on right side. (3) when the sequence is changed in [function3], the file should be loaded again in order to reflect the change.
[akd4344-a] 2007/07 - 13 - 7. [function5 dialog] the register setting that is created by [save] function on main window can be assigned to buttons and executed. when [f5] button is clicked, the following window as shown in figure opens. figure 7. [f5] window 7-1. [open] buttons on left side and [write] button ( 1) click [open] button and select the register setting file (*.akr). (2) click [write] button, then the register setting is executed. 7-2. [save] and [open] buttons on right side [save] : the register setting file names assign can be saved. the file name is *.ak5 . [open] : the register setting file names as sign that are saved in *.ak5 are loaded. 7-3. note (1) all files need to be in same folder used by [save] and [open] function on right side. (3) when the register setting is changed by [save] button in main window, the file should be loaded again in order to reflect the change.
[akd4344-a] 2007/07 - 14 - measurement results [measurement condition] ? measurement unit : audio precision, system two cascade ? mclk : 512fs (fs=44.1khz) / 256fs (fs=96khz) ? bick : 64fs ? fs : 44.1khz / 96khz ? bw : 20hz~20khz (fs=44 .1khz) / 20hz~40khz (fs=96khz) ? bit : 24bit ? power supply : vdd = 3.3v ? interface : psia ? temperature : room [measurement results] parameter results unit dac analog output characteristics lch / rch s/(n+d) (fs=44.1khz, fin=1khz, 0dbfs) (fs=96khz, fin=1khz, 0dbfs) db db d-range (fs=44.1khz, fin=1khz, -60dbfs, a-weighted) (fs=96khz, fin=1khz, -60dbfs, a-weighted) db db s/n (fs=44.1khz, no-input, a-weighted) (fs=96khz, no-input, a-weighted) db db interchannel isolation (fin=1khz, 0dbfs/ no-input) db
[akd4344-a] 2007/07 - 15 - < % " $ 1 m p u g t l ) [ > akm 06/18/07 09:30:43 thd+n vs. input level fs=44.1khz, fin=1khz -100 -70 -98 -96 -94 -92 -90 -88 -86 -84 -82 -80 -78 -76 -74 -72 d b r a -140 +0 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 dbfs ' j h v s f 5 ) % / w t * o q v u - f w f m g j o , ) [
akm 06/18/07 09:28:48 thd+n vs. input freqency fs=44.1khz, fin=0dbfs -100 -70 -98 -96 -94 -92 -90 -88 -86 -84 -82 -80 -78 -76 -74 -72 d b r a 20 20k 50 100 200 500 1k 2k 5k 10k hz ' j h v s f 5 ) % / w t * o q v u ' s f r v f o d z * o q v u - f w f m e # ' 4
[akd4344-a] 2007/07 - 16 - < % " $ 1 m p u g t l ) [ > akm 06/18/07 09:35:13 linearity fs=44.1khz, fin=1khz -140 +0 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 d b r a -140 +0 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 dbfs ' j h v s f - j o f b s j u z g j o , ) [
akm 06/18/07 09:49:36 freqency response fs=44.1khz, fin=0dbfs -1 +1 -0.9 -0.8 -0.7 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 +0 +0.1 +0.2 +0.3 +0.4 +0.5 +0.6 +0.7 +0.8 +0.9 d b r a 2k 20k 4k 6k 8k 10k 12k 14k 16k 18k hz ' j h v s f ' s f r v f o d z 3 f t q p o t f * o q v u - f w f m e # ' 4
[akd4344-a] 2007/07 - 17 - < % " $ 1 m p u g t l ) [ > akm 06/18/07 09:56:53 crosstalk fs=44.1khz -130 -70 -124 -118 -112 -106 -100 -94 -88 -82 -76 d b 10 20k 20 50 100 200 500 1k 2k 5k 10k hz ' j h v s f $ s p t t u b m l g j o , ) [
* o q v u - f w f m e # ' 4 o p j o q v u
akm 06/18/07 10:07:31 fft fs=44.1khz, fin=0dbfs,1khz -160 +0 -150 -140 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 d b r a 10 20k 20 50 100 200 500 1k 2k 5k 10k hz ' j h v s f ' ' 5 1 m p u g j o , ) [
* o q v u - f w f m e # ' 4
[akd4344-a] 2007/07 - 18 - < % " $ 1 m p u g t l ) [ > akm 06/18/07 10:08:53 fft fs=44.1khz, fin=-60dbfs,1khz -160 +0 -150 -140 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 d b r a 10 20k 20 50 100 200 500 1k 2k 5k 10k hz ' j h v s f ' ' 5 1 m p u g j o , ) [
* o q v u - f w f m ? e # ' 4
akm 06/18/07 10:09:30 fft noise floor fs=44.1khz -160 +0 -150 -140 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 d b r a 10 20k 20 50 100 200 500 1k 2k 5k 10k hz ' j h v s f ' ' 5 1 m p u o p j o q v u
[akd4344-a] 2007/07 - 19 - < % " $ 1 m p u g t l ) [ > akm 06/18/07 10:32:35 fft out-of-band noise fs=44.1khz -160 +0 -150 -140 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 d b r a 10 100k 20 50 100 200 500 1k 2k 5k 10k 20k 50k hz ' j h v s f ' ' 5 1 m p u p v u p g c b o e o p j t f
5 ) % / w t * o q v u - f w f m g t , ) [
g j o , ) [ -120 - 70 -117.5 -115 -112.5 -110 -107.5 -105 -102.5 -100 -97.5 -95 -92.5 -90 -87.5 -85 -82.5 -80 -77.5 -75 -72.5 d b r a -140 +0 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 dbfs ' j h v s f 5 ) % / w t * o q v u - f w f m g j o , ) [
[akd4344-a] 2007/07 - 20 - < % " $ 1 m p u g t l ) [ > 5 ) % / w t * o q v u ' s f r v f o d z g t , ) [
* o q v u - f w f m e # ' 4 -120 - 70 -117.5 -115 -112.5 -110 -107.5 -105 -102.5 -100 -97.5 -95 -92.5 -90 -87.5 -85 -82.5 -80 -77.5 -75 -72.5 d b r a 10 40k 20 50 100 200 500 1k 2k 5k 10k 20k hz 5 5 5 5 ' j h v s f 5 ) % / w t * o q v u ' s f r v f o d z * o q v u - f w f m e # ' 4
akm 06/18/07 10:46:53 linearity fs=96khz -140 +0 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 d b r a -140 +0 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 dbfs ' j h v s f - j o f b s j u z g j o , ) [
[akd4344-a] 2007/07 - 21 - < % " $ 1 m p u g t l ) [ > akm 06/18/07 10:49:42 frequency response fs=96khz -1 +1 -0.9 -0.8 -0.7 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 +0 +0.1 +0.2 +0.3 +0.4 +0.5 +0.6 +0.7 +0.8 +0.9 d b r a 2.5k 40k 5k 7.5k 10k 12.5k 15k 17.5k 20k 22.5k 25k 27.5k 30k 32.5k 35k 37.5k hz ' j h v s f ' s f r v f o d z 3 f t q p o t f * o q v u - f w f m e # ' 4
akm 06/18/07 10:52:01 crosstalk fs=96khz -130 -70 -125 -120 -115 -110 -105 -100 -95 -90 -85 -80 -75 d b 10 40k 20 50 100 200 500 1k 2k 5k 10k 20k hz ' j h v s f $ s p t t u b m l g j o , ) [
* o q v u - f w f m e # ' 4 o p j o q v u
[akd4344-a] 2007/07 - 22 - < % " $ 1 m p u g t l ) [ > akm 06/18/07 10:24:00 fft fs=96khz, fin=0dbfs,1khz -160 +0 -150 -140 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 d b r a 10 40k 20 50 100 200 500 1k 2k 5k 10k 20k hz ' j h v s f ' ' 5 1 m p u g j o , ) [
* o q v u - f w f m e # ' 4
akm 06/18/07 10:28:58 fft fs=96khz, fin=-60dbfs,1khz -160 +0 -150 -140 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 d b r a 10 40k 20 50 100 200 500 1k 2k 5k 10k 20k hz ' j h v s f ' ' 5 1 m p u g j o , ) [
* o q v u - f w f m ? e # ' 4
[akd4344-a] 2007/07 - 23 - < % " $ 1 m p u g t l ) [ > akm 06/18/07 10:29:37 fft noise floor fs=96khz -160 +0 -150 -140 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 d b r a 10 40k 20 50 100 200 500 1k 2k 5k 10k 20k hz ' j h v s f ' ' 5 1 m p u o p j o q v u
akm 06/18/07 10:30:24 fft out-of-band noise fs=96khz -160 +0 -150 -140 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 d b r a 10 100k 20 50 100 200 500 1k 2k 5k 10k 20k 50k hz ' j h v s f ' ' 5 1 m p u p v u p g c b o e o p j t f
[akd4344-a] 2007/07 - 24 - revision history date (yy/mm/dd) manual revision board revision reason contents 07/03/15 km087900 0 first edition circuit change change u1 (AK4344): 28pin sop 16pin tssop remove jumper pins: jp1 (test2), jp3 (test1). test2 is open. connect test1 to gnd. 07/04/17 km087901 1 change p3. remove description: (7) jp1 (test2), (8) jp3 (test1). circuit change capacitor between vcom and vss: c3: change: 10uf 4.7uf add capacitor c100: 1nf between j3 (lout) and gnd. add capacitor c101: 1nf between j4 (rout) and gnd. 07/07/02 km087902 2 add add measurement results important notice these products and their specifications are subject to change without notice. when you consider any use or application of these products, please make inquiries the sales office of asahi kasei emd corporati on (akemd) or authorized distributors as to current status of the products. akemd assumes no liability for infringement of any patent, intellectual property, or other rights in the application or use of any information contained herein. any export of these products, or devices or systems containing them, may require an export license or other official approval u nder the law and regulations of the country of export pertaining to customs and tariffs, currency exchange, or strategic materials. akemd products are neither intended nor authorized for use as critical components note1) in any safety, life support, or other hazard related device or system note2) , and akemd assumes no responsibility for such use, except for the use approved with the express written consent by representative director of akemd. as used here: note1) a critical component is one whose failure to function or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. note2) a hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. it is the responsibility of the buyer or distributor of akemd products, who distributes, disposes of, or otherwise places the p roduct with a third party, to notify such third party in advance of the above content and conditions, and the buyer or distributor agr ees to assume any and all responsibility and liability for and hold akemd harmless from any and all claims arising from the use of sai d product in the absence of such notification.
a a b b c c d d e e e e d d c c b b a a AK4344-csn AK4344-cclk AK4344-cdti vdd AK4344-tx AK4344-cdto AK4344-sdti2 AK4344-mclk AK4344-bick AK4344-sdti1 AK4344-lrck AK4344-pdn AK4344-lout AK4344-rout title size document number rev date: sheet of AK4344 2 akd4344-a a4 16 tuesday, june 12, 2007 title size document number rev date: sheet of AK4344 2 akd4344-a a4 16 tuesday, june 12, 2007 title size document number rev date: sheet of AK4344 2 akd4344-a a4 16 tuesday, june 12, 2007 cdto/sdti2 cdto sdti2 + c2 10u + c2 10u c1 0.1u c1 0.1u jp2(3x1) jp2(3x1) cn2 cn2 9 10 11 12 13 14 15 16 + c3 4.7u + c3 4.7u cn1 cn1 1 2 3 4 5 6 7 8 AK4344 u1 AK4344 u1 mclk 1 bick 2 sdti1 3 lrck 4 pdn 5 csn 6 cclk 7 cdti 8 rout 10 lout 11 vcom 12 vss 13 cdto/sdti2 15 vdd 14 test2 16 test1 9
a a b b c c d d e e e e d d c c b b a a ak4112b-erf ak4112b-pdn ak4112b-rx1 ak4112b-mcko1 ak4112b-bick ak4112b-sdto ak4112b-lrck ak4112b-dif0 ak4112b-dif1 ak4112b-dif2 vcc vcc vcc vcc vcc vcc title size document number rev date: sheet of ak4112b 2 akd4344-a a4 26 thursday, may 31, 2007 title size document number rev date: sheet of ak4112b 2 akd4344-a a4 26 thursday, may 31, 2007 title size document number rev date: sheet of ak4112b 2 akd4344-a a4 26 thursday, may 31, 2007 11.2896mhz u2 ak4112b u2 ak4112b dvdd 1 dvss 2 tvdd 3 v/tx 4 xti 5 xto 6 pdn 7 r 8 avdd 9 avss 10 rx1 11 rx2/dif0 12 rx3/dif1 13 rx4/dif2 14 auto 15 p/s 16 fs96 17 erf 18 lrck 19 sdto 20 bick 21 daux 22 mcko2 23 mcko1 24 ocks0/csn 25 ocks1/cclk 26 cm1/cdti 27 cm0/cdto 28 + c4 10u + c4 10u + c10 10u + c10 10u c5 0.1u c5 0.1u + c6 10u + c6 10u r1 18k r1 18k c7 0.1u c7 0.1u c8 5p c8 5p c9 5p c9 5p c11 0.1u c11 0.1u x1 hc-49/u x1 hc-49/u
a a b b c c d d e e e e d d c c b b a a 74lvc541a-pdn AK4344-mclk AK4344-bick AK4344-sdti1 AK4344-lrck AK4344-pdn AK4344-sdti2 ak4112b-mcko1 ext-lrck ak4112b-bick ak4112b-lrck ak4112b-sdto ext-mclk ext-bick port3-sdti2 port3-mclk port3-bick port3-sdti1 port3-lrck vcc title size document number rev date: sheet of 74lvc541a 2 akd4344-a a4 36 thursday, may 31, 2007 title size document number rev date: sheet of 74lvc541a 2 akd4344-a a4 36 thursday, may 31, 2007 title size document number rev date: sheet of 74lvc541a 2 akd4344-a a4 36 thursday, may 31, 2007 dir ext ext ext dir dir mclk bick sdti1 lrck sdti2 port3 gnd jp8 (3x1) jp8 (3x1) c12 0.1u c12 0.1u jp6(2x1) jp6(2x1) r2 51 r2 51 jp4(3x1) jp4(3x1) u3 74lvc541a u3 74lvc541a a1 2 a2 3 a3 4 a4 5 a5 6 a6 7 a7 8 a8 9 g1 1 g2 19 y1 18 y2 17 y3 16 y4 15 y5 14 y6 13 y7 12 y8 11 vcc 20 gnd 10 jp7 (3x1) jp7 (3x1) r4 51 r4 51 jp5(3x1) jp5(3x1) r3 51 r3 51 r5 51 r5 51
a a b b c c d d e e e e d d c c b b a a ext-lrck ext-bick ext-mclk vcc vcc vcc vcc vcc title size document number rev date: sheet of external master clock divider 2 akd4344-a a4 46 thursday, may 31, 2007 title size document number rev date: sheet of external master clock divider 2 akd4344-a a4 46 thursday, may 31, 2007 title size document number rev date: sheet of external master clock divider 2 akd4344-a a4 46 thursday, may 31, 2007 x1 x3 x2 x3 x2 x4 x2 x1 x8 x1 x1 x3 x2 ext ext div clk bcfs lrfs u7d 74hc14 u7d 74hc14 9 8 u7a 74hc14 u7a 74hc14 1 2 14 7 u6 74ac163 u6 74ac163 a 3 qa 14 b 4 qb 13 c 5 qc 12 d 6 qd 11 rco 15 enp 7 ent 10 clk 2 load 9 clr 1 vcc 16 gnd 8 r6 51 r6 51 jp11 (3x2) jp11 (3x2) 1 3 5 6 4 2 u7b 74hc14 u7b 74hc14 3 4 u7f 74hc14 u7f 74hc14 13 12 jp13 (3x2) jp13 (3x2) 1 3 5 6 4 2 u4b 74ac74 u4b 74ac74 d 12 q 9 clk 11 q 8 pr 10 cl 13 vcc 14 gnd 7 u7e 74hc14 u7e 74hc14 11 10 jp10 (4x2) jp10 (4x2) 1 2 3 4 5 6 7 8 j1 bnc-r-pc j1 bnc-r-pc 1 2 3 4 5 u4a 74ac74 u4a 74ac74 d 2 q 5 clk 3 q 6 pr 4 cl 1 vcc 14 gnd 7 jp9 (3x2) jp9 (3x2) 1 3 5 6 4 2 u5 74hc4040 u5 74hc4040 clk 10 rst 11 q1 9 q2 7 q3 6 q4 5 q5 3 q6 2 q7 4 q8 13 q9 12 q10 14 q11 15 q12 1 vcc 16 gnd 8 u7c 74hc14 u7c 74hc14 5 6 jp12 (2x1) jp12 (2x1)
a a b b c c d d e e e e d d c c b b a a 74lvc541a-pdn ak4112b-dif0 ak4112b-dif1 ak4112b-dif2 ak4112b-erf ak4112b-pdn port3-mclk port3-bick port3-lrck port3-sdti1 port3-sdti2 AK4344-csn AK4344-cclk AK4344-cdti AK4344-cdto AK4344-lout AK4344-rout vcc vcc vcc vcc vcc ak4112b-rx1 AK4344-tx vcc vcc vcc vcc vcc title size document number rev date: sheet of input output for digital analog 2 akd4344-a a3 56 tuesday, june 12, 2007 title size document number rev date: sheet of input output for digital analog 2 akd4344-a a3 56 tuesday, june 12, 2007 title size document number rev date: sheet of input output for digital analog 2 akd4344-a a3 56 tuesday, june 12, 2007 h l dif1 dif0 dif2 h l mclk bick sdti1 lrck sdti2 opt bnc up-i/f csn cclk cdti cdto dsp rx1(opt) rx1(bnc) tx(opt) AK4344-pdn ak4112b-pdn ak4112b-mode lout rout rx1 ak4112b-erf j4 bnc-r-pc j4 bnc-r-pc 1 2 3 4 5 r20 470 r20 470 u10 74hct157 u10 74hct157 1a 2 1b 3 2a 5 2b 6 3a 11 3b 10 4a 14 4b 13 a/b 1 g 15 1y 4 2y 7 3y 9 4y 12 vcc 16 gnd 8 r14 10k r14 10k c15 0.1u c15 0.1u r9 10k r9 10k c14 0.1u c14 0.1u r12 220 r12 220 r30 (short) r30 (short) r11 75 r11 75 r17 47k r17 47k r13 10k r13 10k r24 100 r24 100 u9e 74hct04 u9e 74hct04 11 10 c100 1n c100 1n c16 0.1u c16 0.1u r23 470 r23 470 r29 100k r29 100k j2 bnc-r-pc j2 bnc-r-pc 1 2 3 4 5 port2 totx141 port2 totx141 gnd 1 vcc 2 in 3 u8f 74hc14 u8f 74hc14 13 12 7 14 r27 100 r27 100 r16 47k r16 47k r15 47k r15 47k r25 10k r25 10k u9a 74hct04 u9a 74hct04 1 2 j3 bnc-r-pc j3 bnc-r-pc 1 2 3 4 5 r21 100 r21 100 r28 100 r28 100 r7 220 r7 220 port4 a1-10pa-2.54dsa port4 a1-10pa-2.54dsa 1 3 5 7 9 10 8 6 4 2 d1 hsu119 d1 hsu119 k a u9d 74hct04 u9d 74hct04 9 8 u8b 74hc14 u8b 74hc14 3 4 + c13 22u + c13 22u u8e 74hc14 u8e 74hc14 11 10 sw1 ate1d-2m3 sw1 ate1d-2m3 2 1 3 r26 470 r26 470 jp14 (3x1) jp14 (3x1) r8 10k r8 10k r10 470 r10 470 u8c 74hc14 u8c 74hc14 5 6 r22 10k r22 10k sw3 dss103 sw3 dss103 1 2 3 4 5 6 led1 sml-210vt led1 sml-210vt k a u9f 74hct04 u9f 74hct04 13 12 7 14 u9b 74hct04 u9b 74hct04 3 4 r19 10k r19 10k c18 0.1u c18 0.1u u8d 74hc14 u8d 74hc14 9 8 l1 47u l1 47u 1 2 d2 hsu119 d2 hsu119 k a u8a 74hc14 u8a 74hc14 1 2 sw2 ate1d-2m3 sw2 ate1d-2m3 2 1 3 r18 1k r18 1k port1 torx141 port1 torx141 out 1 vcc 3 gnd 2 c101 1n c101 1n port3 a1-10pa-2.54dsa port3 a1-10pa-2.54dsa 1 2 3 4 5 6 7 8 9 10 c19 0.1u c19 0.1u + c17 22u + c17 22u u9c 74hct04 u9c 74hct04 5 6
a a b b c c d d e e e e d d c c b b a a vddi vcci vddi vcci vdd vcc title size document number rev date: sheet of power supply 2 akd4344-a a4 66 thursday, may 31, 2007 title size document number rev date: sheet of power supply 2 akd4344-a a4 66 thursday, may 31, 2007 title size document number rev date: sheet of power supply 2 akd4344-a a4 66 thursday, may 31, 2007 dgnd agnd for 74hc14 x 1, 74hct04 x 1, 74ac74 x 1, 74hc4040 x 1, 74ac163 x 1, 74hc14 x 1 vdd gnd agnd dgnd agnd t_45(black) agnd t_45(black) 1 l3 (short) l3 (short) 1 2 c28 0.1u c28 0.1u c22 0.1u c22 0.1u c27 0.1u c27 0.1u jp15 (2x1) jp15 (2x1) jp16 (2x1) jp16 (2x1) vcc t_45(red) vcc t_45(red) 1 l2 (short) l2 (short) 1 2 c23 0.1u c23 0.1u + c20 47u + c20 47u c24 0.1u c24 0.1u c25 0.1u c25 0.1u + c21 47u + c21 47u c26 0.1u c26 0.1u dgnd t_45(black) dgnd t_45(black) 1 r31 (short) r31 (short) vdd t_45(red) vdd t_45(red) 1 r32 (short) r32 (short)
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